Silicon Device Scaling to the Sub-10-nm Regime

Advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths below 10 nanometers, as compared with current gate lengths in chips that are about 50 nm

Meikei Ieong; Bruce Doris; Jakub Kedzierski; Ken Rim; Min Yang

2004

Key concepts

Scholarcy highlights

  • Advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths below 10 nanometers, as compared with current gate lengths in chips that are about 50 nm
  • Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations
  • We discuss challenges and possible solutions for continued silicon device performance trends down to the sub-10-nm gate regimes

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